ClockTune

Jeng-Liang Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen
As the feature size keeps shrinking and clock frequency increasing, clock design has come to play a crucial role in determining the chip performance and facilitating timing and design convergence. First, clock skew directly affects chip performance in close to a one-to-one ratio since it has to be counted as cycle time penalty. Second, incremental clock tree adjustment enables fast design convergence by avoiding the potentially divergent design iterations. Since designs are subjected to change on a daily basis, the clock trees need to be incrementally adjusted accordingly with minimum changes to ensure acceptable clock skew. Third, since interconnect delay dominates over gate delay, timing plans often cannot be met due to some physical effects. Recently, useful-skew concepts have also been widely proposed to speed up timing convergence in order to compensate for the timing uncertainties resulting from physical layout. From the above analysis, it is crucial to develop clock tuning algorithms that can balance clock skew with minimum adjustments. Buffer-insertion/sizing and wire-sizing techniques are suitable for clock tuning since they involve minimum routing modifications.

ClockTune first takes the input netlist and generates the initial clock routing using the BB+DME algorithm. It then calculates the feasible delay and capacitance load information of each node in a bottom-up fashion. After the desired delay and capacitance load of the root node is chosen, an embedding with target delay and power consumption is selected in a top-down fashion.
PC (Windows based) or SUN
  • ClockTune v1.2 binary and inputs for Windows
  • ClockTune v1.0 binary and inputs for Windows
  • ClockTune v1.0 binary and inputs for UNIX
  • ClockTune v0.9 binary and inputs for Windows
  • ClockTune v0.9 binary and inputs for UNIX
  • Input files:
      ClockTune v1.2 Released
     This version includes simultaneous buffer-insertion/sizing and wire-sizing capability. The ClockTune v1.2 screen shot for r1 is as below.

    Below is a subset of the negative-polarity DC region of r1.
      ClockTune v1.0 Released
     This version includes the wire-sizing capability. The ClockTune v1.0 screen shot for r1 is as below.
      ClockTune v0.9 Released
     This beta version implements the BB+DME algorithm. The program can either randomly generate sink nodes or read an input file, construct the clock tree topology, and output the result in a user specified postscript file. The next version will allow users to nevigate the clock tree and tune the wire widths. Following is the result from r3 using Elmore delay model.
      TECHNICAL SUPPORT
     If you have any technical problem, please email the author Jeng-Liang Tsai (jltsai@cae.wisc.edu) of this tool. Please also report any bug you find to the author. Thanks very much.
      REFERENCE
  • Ran-Song Tsay, "Exact Zero Skew," IEEE Int. Conference on Computer-Aided Design (ICCAD-91), pp. 336- 339, 1991. Nov. 1991.
  • T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Trans. Circuits Syst. -II, pp. 799- 814, 1992.
  • T.-H. Chen, C. Luk, H. Kim, and C. C.-P. Chen, "INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor," 2002 IEEE/ACM international conference on Computer-Aided Design.