The performance and yield of VLSI circuits are affected by path delays as well as clock delays and skews. For clock-tree synthesis researches, it is important to have the complete timing graph of a circuit to evaluate the effectiveness and impacts of the proposed method. However, most of the clock researches rely on Tsay’s 1990 benchmark circuits, r1~r5, which do not contain circuit connectivity information. I have used ISCAS89 benchmark circuits for my clock researches and I’d like to share my experience.
There is no guarantee that the scripts provided here will continue to work because 1) BLIF/GSRC file formats may change and 2) your platform may be incompatible with the platform used to develop these scripts. If the scripts do not work for you, please go ahead and debug/fix them by yourself. If you would like to share your new scripts, please send me a copy and I will update this page. Please do not ask any of the people mentioned in this webpage to fix the scripts for you.
The final goal is to perform placement on ISCAS89 benchmark circuits and extract flip-flop locations as well as circuit connectivity and path delays. It involves the following major steps.
1. Translate ISCAS89 .bench files into Berkeley Logic Interchange Format (BLIF) files.
2. Synthesize ISCAS89 .blif files using Berkeley SIS.
3. Translate synthesized ISCAS89 .blif files into GSRC BookShelf hypergraph files.
4. Place ISCAS89 BookShelf files using UCLA Dragon.
In ISCAS89 benchmark circuits, primary outputs are directly tapped to output nets of logic gates. In my experiments, I assume those primary outputs are fed to output flip-flops. The naming convention of the output flip-flops is “_PO”. For example, the primary output in s27 is tapped to the output net of gate G17. I create a flip-flop _G17 as the primary output.
João Marques Silva generously provides a lot of useful software and scripts on his homepage. The iscas2blif script translates .bench files into .blif files. I have modified iscas2blif to output the list of flip-flops in a separate .fflist file for the following steps. The modified script can be found here.
To execute the script, use
% iscas2blif –c –k design.bench $output_directory
The –k flag keeps the flip-flop outputs in the output list so that SIS will not try to perform state machine reduction and remove some of the flip-flops. There might be a flag to force SIS not to perform state machine reduction.
Before
placement, the benchmark circuits need to be synthesized using a cell
library.
SIS has tons of commands. The simplest way to obtain a synthesized netlist is:
% sis
SIS > read_library lib2all.genlib
SIS > read_blif design.blif
SIS > map
SIS > write_blif –n design.mapped.blif
The -n flag for the write command tells SIS to write out mapped netlist instead of original netlist.
One thing to note is that buffers in the output .blif file will not be mapped to library cells. There might be a flag in SIS to enforce buffer mapping. Yajun Ran provides a script, sweep, to replace unmapped buffers with buffer cell. The command is:
% sweep design.mapped.blif buf_type
In lib2all.genlib, there are three buffer types, buf1x, buf2x and buf4x.
Chung-Kuan Tsai and Yajun Ran provide a script, blif2gsrc, to translate .blif files into GSRC BookShelf hypergraph format. I have modified it to take special care of flip-flops. The command is:
% blif2gsrc design.mapped.blif lib2all.genlib
I use the UCLA Dragon, a public domain placer, for placement. The simpliest way to place a circuit is:
% dragon design.mapped -book